1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a VCDL-based dual loop DLL having an infinite phase shift function.
2. Description of the Related Art
For a high speed operation of a synchronous semiconductor memory device, a delay locked loop (DLL) and a phase locked loop (PLL) are used to remove a delay component of a clock signal.
The DLL is a first system and has a smaller jitter and a faster lock-time than the PLL because a phase noise is not accumulated in the voltage controlled delay line (VCDL). The PLL is a third system and, due to a feedback operation of the PLL, the phase noise is accumulated in a voltage controlled oscillator (VCO). Accordingly, the DLL is widely used for synchronizing a clock signal or generating clock signals having various phases.
FIG. 1 shows a typical DLL. Referring to FIG. 1, a DLL 100 includes a phase detector PD 101, a charge pump CP 102, a loop filter LF 103, a VCDL circuit 104, and a replica buffer 105, to generate an internal clock INT_CLK synchronized with a received external clock EXT_CLK.
The PD 101 compares a degree of delay between the external clock EXT_CLK and the internal clock INT_CLK and transfers a delay difference to the CP 102. The CP 102 generates a control signal VCTL which is proportional to a delay difference between the external clock EXT_CLK and the internal clock INT_CLK, through the LF 103. The LF 103 removes a high frequency component in an output of the PD 101. The VCDL 104, in response to the control signal VCTL, decreases or increases delay of the external clock EXT_CLK. The replica buffer 105 reflects a delay on a signal path along which the generated internal clock INT_CLK is transferred. Accordingly, the DLL 100 matches edges of the external clock EXT_CLK and the internal clock INT_CLK.
The DLL 100 has a limited frequency range in its operation. That is, when the cycle of the external clock signal EXT_CLK is T, to lock the DLL 100, the VCDL circuit 104 and the replica buffer 105 must have a delay time between 0.5 T and 1.5 T during the initial operation which is needed for the operation of the PD 101. Thus, the DLL 100 requires an additional circuit to make the initial delay time to be 0.5 T and 1.5 T.
To solve the frequency range problem of the DLL 100, a dual loop DLL has been developed. As shown in FIG. 2, a dual loop DLL 200 includes a reference DLL 201, a multiplexer 202, a phase interpolator 203, a replica buffer 204, a phase detector PD 205, and a final state machine. The reference DLL 201 has the same constituent elements as those of the DLL 100 of FIG. 1, except for the replica buffer 105.
The conventional DLL 100 of FIG. 1 has a condition that the initial delay time of the VCDL circuit 104 of FIG. 1 has a value between 0.5 T and 1.5 T. In contrast, since the reference DLL 201 does not include the replica buffer 105 of FIG. 1, the VCDL circuit 104 of FIG. 1 only is to be controlled. Thus, the reference DLL 201 is easy to lock regardless of changes in a process, a voltage and a temperature (PVT). In the duel loop DLL 200, the minimum value and the maximum value in the frequency range of the reference DLL 201 are inverse numbers of the maximum delay time and the minimum delay time of the VCDL circuit 104 of FIG. 1. Accordingly, the dual loop DLL 200 has the operation frequency range which is greatly increased than the conventional DLL 100.
The dual loop DLL 200 has an infinite phase shift function which enables a seamless phase change by a phase interpolation function of the phase interpolator 203. That is, the phase of the internal clock INT_CLK that is an output clock of the dual loop DLL 200 can be infinitely increased or decreased without losing the locking of the reference DLL 201. This function makes the dual loop DLL 200 to be used in a plesiochronous clock system or a clock data recovery CDR circuit.
The dual loop DLL 200 initially used an analog phase interpolator. However, a digital phase interpolator is widely used for the dual loop DLL 200 to reduce a slow change of an input signal needed for the phase interpolator and jitter generated during the change of the input signal. However, the minimum jitter of the dual loop DLL 200 using the digital phase interpolator becomes a hindrance to a time unit value of the phase interpolator 203. Therefore, a method of reducing jitter while maintaining a wide frequency operation range and a phase change capability of the dual loop DLL 200 is required.